徐佳唯

博士后

Email：xujiawei@@gdiist.cn

个人简介：

2016年本科毕业于复旦大学信息科学与工程学院电子信息科学与技术专业，2022年于复旦大学取得微电子学与固体电子学博士学位。博士期间围绕类脑芯片与智能系统开展研究，参与国家自然科学基金、上海市新一代人工智能市级重大专项等多项课题，具体研究内容包括存算一体类脑计算仿真系统、低功耗神经网络专用加速器芯片等，完成了高可靠容错SoC系统样机、神经网络处理器FPGA样机与ASIC专用芯片等工作，相关研究成果共发表10余篇学术论文，并申请发明专利4项。

代表论著：

1.     J. Xu, Y. Huan, B. Huang, H. Chu, Y. Jin, L.R. Zheng and Z. Zou, “A Memory-Efficient CNN Accelerator Using Segmented Logarithmic Quantization and Multi-Cluster Architecture,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 6, pp. 2142-2146, June 2021.

2.     J. Xu, Y. Huan, Y. Jin, H. Chu, L. Zheng and Z. Zou, “Base-Reconfigurable Segmented Logarithmic Quantization and Hardware Design for Deep Neural Networks,” in Journal of Signal Processing Systems, vol. 92, no. 11, pp. 1263-1276, 2020.

3.     J. Xu, D. Wang, F. Li, L. Zhang, D. Stathis, Y. Yang, Y. Jin, A. Lansner, A. Hemani, Z. Zou and L.R. Zheng, “A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation,” 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021, pp. 1-4.

4.     J. Xu, Y. Huan, L. Zheng, and Z. Zou, “A Low-Power Arithmetic Element for Multi-Base Logarithmic Computation on Deep Neural Networks,” 2018 31st IEEE International System-on-Chip Conference (SOCC), 2018, pp. 43-48.

5.     D. Wang#, J. Xu#, D. Stathis, L. Zhang, F. Li, A. Lansner, A. Hemani, Y. Yang, P. Herman and Z. Zou, “Mapping the BCPNN Learning Rule to a Memristor Model,” in Frontiers in Neuroscience, vol. 15, p. 1656, 2021. (共同一作)