环宇翔
博士，研究员，研究组组长
Email: yxhuan@@gdiist.cn
个人简介：
环宇翔，研究员，类脑计算架构与超大规模处理系统研究组组长，类脑计算系统研究中心主任。曾于复旦大学取得微电子学与固体电子学博士学位，先后任复旦大学信息科学与工程学院任助理研究员、广东省智能科学与技术研究院副研究员、研究员。环宇翔博士长期围绕领域专用处理架构（Domain-Specific Architecture, DSA）的芯片系统设计和领域应用开展研究，重点聚焦于从芯片到系统的分布式互联处理架构和设计方法的研究，包括可重构可扩展架构的领域专用处理器、深度学习模型的高能效加速和分布式处理、神经拟态专用集成电路和超大规模类脑计算系统等。环宇翔博士在智能院工作期间，带领团队完成了超大规模类脑原型验证系统的研制、多尺度可扩展的类脑智能计算芯片研制。其主持和参与了多项国家级和省部级项目，已累计发表学术论文40余篇，申请发明专利20余项。
类脑计算架构与超大规模处理系统课题组：
本课题组主要面向类脑计算的硬件处理架构和超大规模类脑计算系统设计展开研究，旨在借鉴人脑的信息处理机制，设计具有神经拟态特性的专用处理内核、大规模的芯片互联架构与方法、以及面向全脑尺度千亿神经元规模超级计算系统。课题组将主要聚焦：面向类脑计算的领域专用处理架构与芯片设计，超低延时和高可靠的片上网络互联，面向晶圆级集成芯片的新型片上分布式处理架构和任务调度方法。目标通过“算法-架构-电路”协同设计的方法，实现事件驱动的超大规模芯片计算网络，支持海量处理内核的局部数据共享、异步信息传递和分布式协同处理，最终支撑千亿神经元规模的类脑计算系统的设计构建。
代表论著：
[1] J. Xu, J.Fan, B. Nan, C. Ding, L. Zheng, Z. Zou, Y. Huan*, "ASLog: An Area-Efficient CNN Accelerator for Per-Channel Logarithmic Post-Training Quantization," in IEEE Transactions on Circuits and Systems I: Regular Papers, 2023. (SCI，通信作者)
[2] H. Jia#, Y. Huan#*; C. Ding, Y. Yan, J. Cui, J. Wang, C. Cai, L. Xu, Z. Zou*, L. Zheng*, "ASLog: An Area-Efficient CNN Accelerator for Per-Channel Logarithmic Post-Training Quantization," in IEEE Transactions on Industrial Informatics, 2022. (SCI，共同一作，共同通信作者)
[3] C. Ding#, Y. Huan#*, H. Jia, Y. Yan, F. Yang, L. Liu, M. Shen, Z. Zou and L.R. Zheng, "A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform," in IEEE Transactions on Circuits and Systems I: Regular Papers, 2022. (SCI，共同一作，共同通信作者)
[4] B. Huang#, Y. Huan#*, H. Jia, C. Ding, Y. Yan, B. Huang, L.R. Zheng, and Z. Zou, "AIOC: An All-In-One-Card Hardware Design for Financial Market Trading System," in IEEE Transactions on Circuits and Systems II: Express Briefs, 2022. (SCI，共同一作，共同通信作者)
[5] Y. Jin, B. Huang, Y. Yan; Y. Huan*, J. Xu, S. Li, P. Gope, L. Xu, Z. Zou, and L.R. Zheng, "Edge-based Collaborative Training System for Artificial Intelligence-of-Things," in IEEE Transactions on Industrial Informatics, 2022. (SCI，共同通信作者）
[6] B. Huang#, Y. Huan#*, H. Chu, J. Xu, L.R. Zheng, and Z. Zou, “IECA: An In-Execution Configuration CNN Accelerator With 30.55 GOPS/mm² Area Efficiency,” in IEEE Transactions on Circuits and Systems I: Regular Papers, 2021. (SCI，共同一作，通信作者)
[7] J. Xu#, Y. Huan#, B. Huang, H. Chu, Y. Jin, L.R. Zheng, Z. Zou, “A Memory-Efficient CNN Accelerator Using Segmented Logarithmic Quantization and Multi-Cluster Architecture,” in IEEE Transactions on Circuits and Systems II: Express Briefs, 2020. (SCI，共同一作)
[8] Y. Huan, N. Ma, J. Mao, S. Blixt, Z. Lu, Z. Zou and L. R. Zheng, “A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications,” in IEEE Transactions on Circuits and Systems I: Regular Papers, 2016. (SCI)
[9] Y. Jin, J. Cai, J. Xu, Y. Huan*, Y. Yan, B. Huang, Y. Guo, L.R. Zheng, Z. Zou, “Self-aware distributed deep learning framework for heterogeneous IoT edge devices,” Future Generation Computer Systems, 2021. (SCI，通信作者)
[10] W. Li, H. Chu, B. Huang, Y. Huan*, L.R. Zheng, Z. Zou, “Enabling on-device classification of ECG with compressed learning for health IoT,” Microelectronics Journal, 2021. (SCI，通信作者)
[11] J. Xu#, Y. Huan#, B. Huang, H. Chu, Y. Jin, L.R. Zheng, Z. Zou, “Base-Reconfigurable Segmented Logarithmic Quantization and Hardware Design for Deep Neural Networks,” in Journal of Signal Processing Systems, 2020. (SCI，共同一作)
[12] Y. Huan, J. Xu, L. Zheng, H. Tenhunen and Z. Zou, “A 3D Tiled Low Power Accelerator for Convolutional Neural Network,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018. (EI)
