Chen Ding
Assistant Engineer
Email: dingchen@@gdiist.cn
Research Interests:
Design of special computing chips for brain-like and neural networks
Personal Profile:
He graduated from Xidian University with a bachelor's degree in microelectronics science and engineering in 2018 and a doctorate degree in electronic information from Fudan University in 2024. During his Ph.D., he focused on the design of a communication-centric neural network accelerator architecture. During his Ph.D., he participated in many projects such as the National Natural Science Foundation of China and the Shanghai Municipal Major Project of New Generation Artificial Intelligence. The specific research contents include the design of brain-inspired computing system based on mixed-mode routing, and the design of special computing chips for neural networks with high computing unit utilization based on network-on-chip. During his Ph.D., he completed the FPGA prototype of the million-neuron-level brain-like simulation and computing platform, as well as the FPGA prototype prototype and ASIC chip design tape-out of the neural network computing acceleration system based on the network-on-chip. A total of 7 academic papers have been published and 2 invention patents have been applied for.
Representative publications:
1. C. Ding, H. Ji, B. Huang, Y. Huan, L. -R. Zheng and Z. Zou, "Communication-Aware and Resource-Efficient NoC-Based Architecture for CNN Acceleration," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 14, no. 3, pp. 440-454, Sept. 2024.
2. C. Ding, Y. Huan, H. Jia, Y. Yan, et al., “A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform”. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 69, no. 5, pp. 1990-2001, May 2022.
3. C. Ding, Y. Huan, H. Jia, et al., "An Ultra-Low Latency Multicast Router for Large-Scale Multi-Chip Neuromorphic Processing," 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), Washington DC, DC, USA, 2021
4. C. Ding, Y. Huan, L. Zheng and Z. Zou, "Dynamic Precision Multiplier For Deep Neural Network Accelerators," 2020 IEEE 33rd International System-on-Chip Conference (SOCC), Las Vegas, NV, USA, pp. 180-184, 2020.
5. H. Jia, Y. Huan, C. Ding, Y. Yan, et al, "A Domain-Specific Accelerator for Ultra-low Latency Market Data Distribution System," in lEEE Transactions on industrial Informatics, vol. 19, no.4,pp.5465-5475,April 2023.
6. J. Xu, J. Fan, B. Nan, C. Ding, et al., "ASLog: An Area-Efficient CNN Accelerator for Per-Channel Logarithmic Post-Training Quantization," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 12, pp. 5380-5393, Dec. 2023.
7. B. Huang, Y. Huan, H. Jia, C. Ding, et al., "AIOC: An All-in-One-Card Hardware Design for Financial Market Trading System," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 9, pp. 3894-3898, Sept. 2022
