HUAN Yuxiang
Ph.D., Principal Investigator
Email: yxhuan@@gdiist.cn
Personal Profile:
Huan Yuxiang is a Principal Investigator of the Lab of the Brain-inspired Computing Architecture and Large-Scale Processing Systems, as well as the director of the Brain-inspired Computing Systems Research Center. He obtained his Ph.D. in Microelectronics from Fudan University. Dr. Huan has long been engaged in research on System-on-Chip design and Domain-Specific Architecture (DSA), focusing on distributed processing architecture and brain-inspired processing chips. His research includes domain-specific accelerator with reconfigurable and scalable architectures, distributed processing of deep learning models, neuromorphic processors, and ultra-large-scale brain-inspired computing systems.
During his work at the Guangdong Institute of Intelligent Science and Technology, Dr. HUAN led his team in completing the development of an ultra-large-scale brain-inspired prototype verification system and several scalable brain-inspired computing chips.
Lab of the Brain-inspired Computing Architecture and Large-Scale Processing Systems:
This lab primarily focuses on hardware processing architectures for brain-inspired computing and the design of ultra-large-scale brain-inspired computing systems. The aim is to draw inspiration from the information processing mechanisms of the human brain to design specialized processing cores with brain-inspired characteristics, large-scale chip interconnection architectures and methods, and computing systems capable of simulating brain-scale networks of hundreds of billions of neurons. The lab will mainly concentrate on:
1） Domain-specific processing architectures and chip designs for brain-inspired computing
2） Ultra-low latency and highly reliable on-chip network interconnections
3） Novel distributed processing architectures and task scheduling methods for large-scale brain simulation
The goal is to achieve an event-driven and large-scale multi-chip system through the co-optimization of "algorithm-architecture-circuit". This system will support local data sharing, asynchronous information transmission, and distributed collaborative processing among massive processing cores, ultimately supporting the design and construction of brain simulation systems at the scale of hundreds of billions of neurons.
Representative publications
[1] J. Xu, J.Fan, B. Nan, C. Ding, L. Zheng, Z. Zou, Y. Huan*, "ASLog: An Area-Efficient CNN Accelerator for Per-Channel Logarithmic Post-Training Quantization," in IEEE Transactions on Circuits and Systems I: Regular Papers, 2023. (SCI)
[2] H. Jia#, Y. Huan#*; C. Ding, Y. Yan, J. Cui, J. Wang, C. Cai, L. Xu, Z. Zou*, L. Zheng*, "ASLog: An Area-Efficient CNN Accelerator for Per-Channel Logarithmic Post-Training Quantization," in IEEE Transactions on Industrial Informatics, 2022. (SCI)
[3] C. Ding#, Y. Huan#*, H. Jia, Y. Yan, F. Yang, L. Liu, M. Shen, Z. Zou and L.R. Zheng, "A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform," in IEEE Transactions on Circuits and Systems I: Regular Papers, 2022. (SCI)
[4] B. Huang#, Y. Huan#*, H. Jia, C. Ding, Y. Yan, B. Huang, L.R. Zheng, and Z. Zou, "AIOC: An All-In-One-Card Hardware Design for Financial Market Trading System," in IEEE Transactions on Circuits and Systems II: Express Briefs, 2022. (SCI)
[5] Y. Jin, B. Huang, Y. Yan; Y. Huan*, J. Xu, S. Li, P. Gope, L. Xu, Z. Zou, and L.R. Zheng, "Edge-based Collaborative Training System for Artificial Intelligence-of-Things," in IEEE Transactions on Industrial Informatics, 2022. (SCI）
[6] B. Huang#, Y. Huan#*, H. Chu, J. Xu, L.R. Zheng, and Z. Zou, “IECA: An In-Execution Configuration CNN Accelerator With 30.55 GOPS/mm² Area Efficiency,” in IEEE Transactions on Circuits and Systems I: Regular Papers, 2021. (SCI)
[7] J. Xu#, Y. Huan#, B. Huang, H. Chu, Y. Jin, L.R. Zheng, Z. Zou, “A Memory-Efficient CNN Accelerator Using Segmented Logarithmic Quantization and Multi-Cluster Architecture,” in IEEE Transactions on Circuits and Systems II: Express Briefs, 2020. (SCI)
[8] Y. Huan, N. Ma, J. Mao, S. Blixt, Z. Lu, Z. Zou and L. R. Zheng, “A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications,” in IEEE Transactions on Circuits and Systems I: Regular Papers, 2016. (SCI)
[9] Y. Jin, J. Cai, J. Xu, Y. Huan*, Y. Yan, B. Huang, Y. Guo, L.R. Zheng, Z. Zou, “Self-aware distributed deep learning framework for heterogeneous IoT edge devices,” Future Generation Computer Systems, 2021. (SCI)
[10] W. Li, H. Chu, B. Huang, Y. Huan*, L.R. Zheng, Z. Zou, “Enabling on-device classification of ECG with compressed learning for health IoT,” Microelectronics Journal, 2021. (SCI)
[11] J. Xu#, Y. Huan#, B. Huang, H. Chu, Y. Jin, L.R. Zheng, Z. Zou, “Base-Reconfigurable Segmented Logarithmic Quantization and Hardware Design for Deep Neural Networks,” in Journal of Signal Processing Systems, 2020. (SCI)
[12] Y. Huan, J. Xu, L. Zheng, H. Tenhunen and Z. Zou, “A 3D Tiled Low Power Accelerator for Convolutional Neural Network,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018. (EI)
